This invention relates to MIS-type semiconductor memory devices. More particularly, it pertains to VLSI, very large scale integration.
Flash-type EEPROMs (electrically erasable programmable ROMs) have been known as a VLSI semiconductor memory circuit (VLSI Symp. pp., 1991 by H. Kume et al). With reference to FIG. 30 (a and b), a conventional semiconductor memory circuit will be illustrated. FIG. 30a is a cross-sectional view of a conventional semiconductor memory device structure. Formed on a p-type semiconductor substrate a is a first SiO.sub.2 layer b1 (i.e., an oxide insulating layer) over which lie a floating gate formed of a Si polycrystalline layer, a second SiO.sub.2 layer b2 and a control gate electrode c formed of a Si polycrystalline layer. On the surface region of the semiconductor substrate a, a drain region e is formed at one edge of the first SiO.sub.2 layer b1 and a source region f, at the other edge. Furthermore, a metal layer g of an aluminum, which forms a bit line via an interlayer dielectric h, is formed.
A flash-type EEPROM, as described above, incorporates therein no capacitors, so that it compares favorably with a DRAM (dynamic RAM) in that it has positive possibilities of accomplishing a VLSI. FIG. 30b shows an example of a circuit wiring structure of a conventional EEPROM. Bit lines D0 and D1 are tied to respective drains e of each of memory cells A, B, C and D. Connected to respective control gate electrodes c of each of the memory cells are word lines W0 and W1. And a source line S is tied to a source f of each memory cell. As is depicted in FIG. 30b, a flash-type EEPROM employs a simpler circuit structure than a DRAM. The following table shows individual voltages of the W0, W1, S, D0 and D1 when executing ERASE, "1" WRITE or READ operation for the memory cell A.
TABLE 1 ______________________________________ W0 W1 S D0 D1 ______________________________________ ERASE -9 5 5 FLOATING FLOATING WRITE 10 0 0 4 0 READ 5 0 0 1 0 ______________________________________
For a conventional flash-type EEPROM to achieve a large scale integration as well as a high-speed operation, two erase methods have been used, which are a sector erase method of deleting a plurality of memory cells as a single unit and a block unit batch erase method.
Japanese Patent Publication No. 3-166768 discloses a drain region i of a first conductivity type (p-type) and a source region J of a second conductivity type (n-type) which are selectively formed on a semiconductor substrate of a first conductivity type (p-type) (see FIG. 31). An insulating layer k which is thick enough to cause tunneling is formed in a manner such that it extends from the drain region 1 to the source region j. Formed on the insulating layer k are an information storage layer 1 which traps therein an electric charge, and a gate electrode m. When a write operation is executed, a given high voltage is placed to the gate electrode m to cause band-to-band tunneling in a surface portion 11 of the drain region 1 positioned just under the gate electrode m. An electron, generated by this tunneling phenomenon, passes through the insulating layer k so that it will be trapped in the information storage layer 1. In this way, nonvolatile information is stored. On the other hand, in some prior art techniques, the information thus stored is read out of the information storage layer 1 by applying a given read voltage to the gate electrode m to detect whether an ON state occurs due to the generation of band-to-band tunneling in the surface portion il of the drain region i positioned just under the gate electrode m. In other words, by getting rid of channel effect, such techniques intend to shorten the length of a channel to achieve a large scale integration and a high speed read operation.
Additionally, Japanese Patent Publication No. 2-106068 discloses a technique. As shown in FIG. 33a, a source region p and a drain region q, each of which is of a second conductivity type, are formed on a semiconductor substrate o of a first conductivity type. Extending from one edge of the source region p to one edge of the drain region q is a SiO.sub.2 layer r over which lies a gate electrode t. An ion implantation region s is formed at one side of the SiO.sub.2 layer r facing the semiconductor substrate o by mean of the Si (or the group IV elements such as Ge) ion implantation method using accelerating energy of about 15 keV. In this prior art, the implantation and emission of charges to and from the ion implantation region s is controlled so that the ion implantation region s is given a nonvolatile memory function. That is, this prior art uses hysteresis phenomenons, as shown in FIG. 33b in which the abscissa indicates a gate to source voltage Vgs while the ordinate indicates a drain current Id. With a drain to source voltage Vds and a substrate bias Vsub set to 0.1 V and 0 V respectively, there is a threshold voltage difference between "when sweeping the gate to source voltage Vgs from -5 to 5 V (which is indicated by curve CO)" and "when sweeping the same the other way round, that is, from 5 to -5 (which is indicated by curve C1)".
However, the word line in the foregoing flash-type EEPROM requires a negative voltage, -9 V which is above TTL levels. Furthermore, four values, namely voltages 0 V, 5 V, 10 V including a negative voltage, are required, as shown in Table 1. In addition thereto, the bit line also requires four values, namely voltages 0 V, 1 V, 4 V including a floating voltage. These are obstacles not only to the realization of a high speed operation, but also to the realization of a large scale integration, since related peripheral circuits including a power circuit inevitably become large. In addition, since a source line requires two values, 0 V and 5 V, this also causes additional difficulties in achieving a high speed operation and a large scale integration.
Of all of the conventional technologies, DRAMs have been known as a largest scale integrated semiconductor memory circuit, which are capable of executing a READ or WRITE operation per bit. In DRAMs, however, a read operation is done in a destructive manner, resulting in destroying the data stored in every memory cell sharing a common word line with a certain memory cell that has been selected in carrying out a READ or WRITE operation. This necessitates such an arrangement that a sense amplifier must be connected to each bit line in order that the data destroyed is rewritten to all of the memory cells sharing a common word line with the selected memory cell while READ or WRITE operation is being executed. Further, as data holding time is very short (about one second), DRAMs require refresh operations. Such also causes problems such as a very slow speed operation and the increase of power consumption.
SRAMs (static RAM) have been recognized as a semiconductor memory circuit with a shortest access time, which are capable of executing both READ and WRITE operations per bit. In SRAMs, a READ operation is done in a non-destructive manner, and no refresh operations are required unlike DRAMs. A 1-bit memory cell of the SRAM, however, is composed of four or more MOS transistors. In addition, since two bit lines are connected to a single memory cell, this causes difficulties in achieving a large scale integration. Generally, the degree of integration of SRAMs is a quarter of that of DRAMs, and the memory cell of SRAMs requires power supply even in a data holding state. This inevitably leads to the increase of power consumption.
The former Japanese Patent Publication is able to store information in a nonvolatile state and adopts a memory cell provided with one transistor. Because of such features, this prior art may have some advantages to realize a larger scale integration over DRAMs and SRAMs.
In the above prior art, the drain region i and source region j have a different conductivity type. Because of this, a source region leakage current (indicated by solid line) and a drain region leakage current (indicated by broken line) are generated, as shown in FIG. 32. To prevent these unwanted currents occurring, it is necessary to form, for example, a deep insulating layer or the like, which however is not deemed practical.
For the invention of the latter Japanese Patent Publication, the drain region q and the source region p have the same conductivity type, so that the foregoing unfavorable leakage currents may be easily avoided. Instead, punch-through, however, occurs when the length of a gate is shortened due to short channel effect, which causes difficulties in improving the degree of integration.